K60P100M100SF2RM Datasheet, PDF (253/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 11 Port control and interrupts (PORT)
11.2 External signal description
Table 11-1. Signal properties
Name
Function
I/O
PORTx[31:0]
External interrupt
I/O
Reset
Pull
0
-
NOTE
Not all pins within each port are implemented on each device.
11.3 Detailed signal descriptions
Table 11-2. PORTx interface-detailed signal descriptions
Signal
PORTx[31:0]
I/O
I/O
External interrupt.
State meaning
Timing
Description
Asserted-pin is logic one.
Negated-pin is logic zero.
Assertion-may occur at any
time and can assert
asynchronously to the system
clock.
Negation-may occur at any
time and can assert
asynchronously to the system
clock.
11.4 Memory map and register definition
Any read or write access to the PORT memory space that is outside the valid memory
map results in a bus error. All register accesses complete with zero wait states.
PORT memory map
Absolute
address
(hex)
Register name
4004_9000 Pin Control Register n (PORTA_PCR0)
4004_9004 Pin Control Register n (PORTA_PCR1)
4004_9008 Pin Control Register n (PORTA_PCR2)
Width
(in bits)
Access
Reset value
Section/
page
32
R/W 0000_0000h 11.4.1/260
32
R/W 0000_0000h 11.4.1/260
32
R/W 0000_0000h 11.4.1/260
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
253