K60P100M100SF2RM Datasheet, PDF (909/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 38 Programmable Delay Block (PDB)
38.1.6 Modes of Operation
PDB ADC trigger operates in the following modes.
Disabled: Counter is off, all pre-trigger and trigger outputs are low if PDB is not in back-
to-back operation of Bypass mode.
Debug: Counter is paused when processor is in debug mode, the counter for dac trigger
also paused in Debug mode.
Enabled One-Shot: Counter is enabled and restarted at count zero upon receiving a
positive edge on the selected trigger input source or software trigger is selected and
SC[SWTRIG] is written with 1. In each PDB channel, an enabled pre-trigger asserts once
per trigger input event; the trigger output asserts whenever any of pre-triggers is asserted.
Enabled Continuous: Counter is enabled and restarted at count zero. The counter is
rolled over to zero again when the count reaches the value specified in the modulus
register, and the counting is restarted. This enables a continuous stream of pre-triggers/
trigger outputs as a result of a single trigger input event.
Enabled Bypassed: The pre-trigger and trigger outputs assert immediately after a
positive edge on the selected trigger input source or software trigger is selected and
SC[SWTRIG] is written with 1, that is the delay registers are bypassed. It is possible to
bypass any one or more of the delay registers; therefore this mode can be used in
conjunction with One-Shot or Continuous mode.
38.2 PDB Signal Descriptions
This table shows the detailed description of the external signal.
Table 38-1. PDB Signal Descriptions
Signal
Description
I/O
EXTRG
External trigger input source. If the PDB is enabled and external trigger
I
input source is selected, a positive edge on the EXTRG signal resets and
starts the counter.
38.3 Memory Map and Register Definition
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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