K60P100M100SF2RM Datasheet, PDF (406/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
Offset
0x60
0x64
0x68
0x6C
Register [31:28] [27:24] [23:20] [19:16] [15:12]
[11:8]
[7:4]
[3:0]
PACRM PACR96 PACR97 PACR98 PACR99 PACR100 PACR101 PACR102 PACR103
PACRN PACR104 PACR105 PACR106 PACR107 PACR108 PACR109 PACR110 PACR111
PACRO PACR112 PACR113 PACR114 PACR115 PACR116 PACR117 PACR118 PACR119
PACRP PACR120 PACR121 PACR122 PACR123 PACR124 PACR125 PACR126 PACR127
Addresses: AIPS0_PACRA is 4000_0000h base + 20h offset = 4000_0020h
AIPS0_PACRB is 4000_0000h base + 24h offset = 4000_0024h
AIPS0_PACRC is 4000_0000h base + 28h offset = 4000_0028h
AIPS0_PACRD is 4000_0000h base + 2Ch offset = 4000_002Ch
AIPS1_PACRA is 4008_0000h base + 20h offset = 4008_0020h
AIPS1_PACRB is 4008_0000h base + 24h offset = 4008_0024h
AIPS1_PACRC is 4008_0000h base + 28h offset = 4008_0028h
AIPS1_PACRD is 4008_0000h base + 2Ch offset = 4008_002Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R0
0
0
0
0
0
0
0
W
Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
AIPSx_PACRn field descriptions
Field
31
Reserved
30
SP0
Description
This read-only field is reserved and always has the value zero.
Supervisor protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates.
29
WP0
0 This peripheral does not require supervisor privilege level for accesses.
1 This peripheral requires supervisor privilege level for accesses.
Write protect
Determines whether the peripheral allows write accesss. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0 This peripheral allows write accesses.
1 This peripheral is write protected.
28
Trusted protect
TP0
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0 Accesses from an untrusted master are allowed.
1 Accesses from an untrusted master are not allowed.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
406
Freescale Semiconductor, Inc.