K60P100M100SF2RM Datasheet, PDF (53/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Section Number
Title
Page
Chapter 53
Integrated interchip sound (I2S)
53.1 Introduction...................................................................................................................................................................1675
53.1.1 Block diagram..............................................................................................................................................1675
53.1.2 Features........................................................................................................................................................1676
53.1.3 Modes of operation......................................................................................................................................1677
53.2 I2S signal descriptions..................................................................................................................................................1679
53.3 Memory map/register definition...................................................................................................................................1683
53.3.1 I²S Transmit Data Registers 0 (I2Sx_TX0).................................................................................................1685
53.3.2 I²S Transmit Data Registers 1 (I2Sx_TX1).................................................................................................1685
53.3.3 I²S Receive Data Registers 0 (I2Sx_RX0)...................................................................................................1686
53.3.4 I²S Receive Data Registers 1 (I2Sx_RX1)...................................................................................................1686
53.3.5 I²S Control Register (I2Sx_CR)...................................................................................................................1687
53.3.6 I²S Interrupt Status Register (I2Sx_ISR).....................................................................................................1690
53.3.7 I²S Interrupt Enable Register (I2Sx_IER)....................................................................................................1695
53.3.8 I²S Transmit Configuration Register (I2Sx_TCR).......................................................................................1699
53.3.9 I²S Receive Configuration Register (I2Sx_RCR)........................................................................................1701
53.3.10 I²S Transmit Clock Control Registers (I2Sx_TCCR)..................................................................................1703
53.3.11 I²S Receive Clock Control Registers (I2Sx_RCCR)...................................................................................1705
53.3.12 I²S FIFO Control/Status Register (I2Sx_FCSR)..........................................................................................1706
53.3.13 I²S AC97 Control Register (I2Sx_ACNT)...................................................................................................1712
53.3.14 I²S AC97 Command Address Register (I2Sx_ACADD).............................................................................1713
53.3.15 I²S AC97 Command Data Register (I2Sx_ACDAT)...................................................................................1714
53.3.16 I²S AC97 Tag Register (I2Sx_ATAG)........................................................................................................1714
53.3.17 I²S Transmit Time Slot Mask Register (I2Sx_TMSK)................................................................................1715
53.3.18 I²S Receive Time Slot Mask Register (I2Sx_RMSK).................................................................................1715
53.3.19 I²S AC97 Channel Status Register (I2Sx_ACCST).....................................................................................1716
53.3.20 I²S AC97 Channel Enable Register (I2Sx_ACCEN)...................................................................................1716
53.3.21 I²S AC97 Channel Disable Register (I2Sx_ACCDIS).................................................................................1717
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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