K60P100M100SF2RM Datasheet, PDF (410/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
AIPSx_PACRn field descriptions (continued)
Field
4
TP6
Trusted protect
Description
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates .
3
Reserved
2
SP7
0 Accesses from an untrusted master are allowed.
1 Accesses from an untrusted master are not allowed.
This read-only field is reserved and always has the value zero.
Supervisor protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates .
1
WP7
0 This peripheral does not require supervisor privilege level for accesses.
1 This peripheral requires supervisor privilege level for accesses.
Write protect
Determines whether the peripheral allows write accesss. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0 This peripheral allows write accesses.
1 This peripheral is write protected.
0
Trusted protect
TP7
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0 Accesses from an untrusted master are allowed.
1 Accesses from an untrusted master are not allowed.
19.2.3 Peripheral Access Control Register (AIPSx_PACRn)
Each of the peripherals has a four-bit PACR[0:127] field which defines the access levels
supported by the given module. Eight PACR fields are grouped together to form a 32-bit
PACR[A:P] register:
• PACRA-P define the access levels for the 128 peripherals
The peripheral assignments to each PACR register is defined by the memory map slot
that the peripherals are assigned.See the device's Memory Map details for the
assignments for your particular device.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
410
Freescale Semiconductor, Inc.