K60P100M100SF2RM Datasheet, PDF (1702/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map/register definition
I2Sx_RCR field descriptions (continued)
Field
Description
This bit controls the direction and source of the receive frame sync signal. Internally generated frame sync
signal is sent out through the SRFS port and external frame sync is taken from the same port.
5
RXDIR
0 Frame Sync is external.
1 Frame Sync generated internally.
Receive Clock Direction.
This bit controls the direction and source of the clock signal used to clock the RXSR. Internally generated
clock is output through the SRCK port. External clock is taken from this port.
4
RSHFD
0 Receive Clock is external.
1 Receive Clock generated internally.
Receive Shift Direction.
This bit controls whether the MSB or LSB will be received first in a sample.
NOTE: The CODEC device labels the MSB as bit 0, whereas the Core labels the LSB as bit 0.
Therefore, when using a standard CODEC, Core MSB (CODEC LSB) is shifted in first (RSHFD
cleared).
3
RSCKP
0 Data received MSB first.
1 Data received LSB first.
Receive Clock Polarity.
This bit controls which bit clock edge is used to latch in data for the receive section.
2
RFSI
0 Data latched on falling edge of bit clock.
1 Data latched on rising edge of bit clock.
Receive Frame Sync Invert.
This bit controls the active state of the frame sync I/O signal for the receive section of I²S.
1
RFSL
0 Receive frame sync is active high.
1 Receive frame sync is active low.
Receive Frame Sync Length.
This bit controls the length of the frame sync signal to be generated or recognized for the receive section.
The length of a word-long frame sync is same as the length of the data word selected by WL[3:0].
0
REFS
0 Receive frame sync is one-word long.
1 Receive frame sync is one-clock-bit long.
Receive Early Frame Sync.
This bit controls when the frame sync is initiated for the receive section. The frame sync is disabled after
one bit-for-bit length frame sync and after one word-for-word length frame sync.
0 Receive frame sync initiated as the first bit of data is received.
1 Receive frame sync is initiated one bit before the data is received.
1702
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.