K60P100M100SF2RM Datasheet, PDF (1429/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

49.4.4.3 Continuous Selection Format
Chapter 49 SPI (DSPI)
Some peripherals must be deselected between every transfer. Other peripherals must
remain selected between several sequential serial transfers. The Continuous Selection
Format provides the flexibility to handle the following case. The Continuous Selection
Format is enabled for the SPI Configuration by setting the CONT bit in the SPI
command. The behavior of the PCS signals in the configurations is identical so only SPI
Configuration will be described.
When the CONT bit = 0, the DSPI drives the asserted Chip Select signals to their idle
states in between frames. The idle states of the Chip Select signals are selected by the
PCSISn bits in the MCR. The following timing diagram is for two four-bit transfers with
CPHA = 1 and CONT = 0.
SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
Master SIN
PCSx
t_CSC
t _ASC t_{DT tCSC}
tCSC ₌ PCS to SCK dela
t _{ASC = After SCK delay}
t_{DT =} Delay after Transfer (minimum CS negation time)
Figure 49-96. Example of Non-Continuous Format (CPHA=1, CONT=0)
When the CONT bit = 1, the PCS signal remains asserted for the duration of the two
transfers. The Delay between Transfers (t_DT) is not inserted between the transfers. The
following figure shows the timing diagram for two four-bit transfers with CPHA = 1 and
CONT = 1.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1429