K60P100M100SF2RM Datasheet, PDF (527/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 23 Watchdog Timer (WDOG)
WDOG_STCTRLH field descriptions (continued)
Field
Description
0 Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test.
1 Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for
operation and are compared for time-out against the corresponding byte of the programmed time-out
value. Select the byte through BYTESEL[1:0] for testing.
10
TESTWDOG
Puts the watchdog in the functional test mode. In this mode the watchdog timer and the associated
compare and reset generation logic is tested for correct operation. The clock for the timer is switched from
the main watchdog clock to the fast clock input for watchdog functional test. The TESTSEL bit selects the
test to be run.
9
Reserved
This read-only field is reserved and always has the value zero.
8
STNDBYEN
Enables or disables WDOG in Standby mode.
0 WDOG is disabled in system Standby mode.
1 WDOG is enabled in system Standby mode.
7
WAITEN
Enables or disables WDOG in wait mode.
0 WDOG is disabled in CPU wait mode.
1 WDOG is enabled in CPU wait mode.
6
STOPEN
Enables or disables WDOG in stop mode.
0 WDOG is disabled in CPU stop mode.
1 WDOG is enabled in CPU stop mode.
5
DBGEN
Enables or disables WDOG in Debug mode.
0 WDOG is disabled in CPU Debug mode.
1 WDOG is enabled in CPU Debug mode.
4
Enables updates to watchdog write once registers, after initial configuration window (WCT) closes,
ALLOWUPDATE through unlock sequence.
3
WINEN
2
IRQRSTEN
0 No further updates allowed to WDOG write once registers.
1 WDOG write once registers can be unlocked for updating.
Enable windowing mode.
0 Windowing mode is disabled.
1 Windowing mode is enabled.
Used to enable the debug breadcrumbs feature. A change in this bit is updated immediately, as opposed
to updating after WCT.
1
CLKSRC
0
WDOGEN
0 WDOG time-out generates reset only.
1 WDOG time-out initially generates an interrupt. After WCT time, it generates a reset.
Selects clock source for the WDOG timer and other internal timing operations.
0 Dedicated clock source selected as WDOG clock (LPO Oscillator).
1 WDOG clock sourced from alternate clock source.
Enables or disables the WDOG’s operation. In the disabled state, the watchdog timer is kept in the reset
state, but the other exception conditions can still trigger a reset/interrupt. A change in the value of this bit
must be held for more than one WDOG_CLK cycle for the WDOG to be enabled or disabled.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
527