K60P100M100SF2RM Datasheet, PDF (610/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register descriptions
27.4.9 Cache Data Storage (lower word) (FMC_DATAW0SL)
The cache of 64-bit entries is a 4-way, set-associative cache with 8 sets. The ways are
numbered 0-3 and the sets are numbered 0-7. In DATAWxSyU and DATAWxSyL, x
denotes the way, y denotes the set, and U and L represent upper and lower word,
respectively. This section represents data for the lower word (bits [31:0]) of all 8 sets
(n=0-7) in way 0.
Addresses: FMC_DATAW0S0L is 4001_F000h base + 204h offset = 4001_F204h
FMC_DATAW0S1L is 4001_F000h base + 20Ch offset = 4001_F20Ch
FMC_DATAW0S2L is 4001_F000h base + 214h offset = 4001_F214h
FMC_DATAW0S3L is 4001_F000h base + 21Ch offset = 4001_F21Ch
FMC_DATAW0S4L is 4001_F000h base + 224h offset = 4001_F224h
FMC_DATAW0S5L is 4001_F000h base + 22Ch offset = 4001_F22Ch
FMC_DATAW0S6L is 4001_F000h base + 234h offset = 4001_F234h
FMC_DATAW0S7L is 4001_F000h base + 23Ch offset = 4001_F23Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
data[31:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
FMC_DATAW0SnL field descriptions
Field
31–0
data[31:0]
Bits [31:0] of data entry
Description
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
610
Freescale Semiconductor, Inc.