K60P100M100SF2RM Datasheet, PDF (266/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
PORTx_DFWR field descriptions
Field
31–5
Reserved
4–0
FILT
Description
This read-only field is reserved and always has the value zero.
Filter Length
The digital filter configuration is valid in all digital pin muxing modes. Configures the maximum size of the
glitches (in clock cycles) the digital filter absorbs for enabled digital filters. Glitches that are longer than
this register setting (in clock cycles) will pass through the digital filter, while glitches that are equal to or
less than this register setting (in clock cycles) will be filtered. Changing the filter length should only be
done after disabling all enabled filters.
11.5 Functional description
11.5.1 Pin control
The lower half of the pin control register configures the following functions for each pin
within the 32-bit port. These functions apply across all digital pin muxing modes and
individual peripherals do not override the configuration in this register (for example, if an
I²C function is enabled on a pin then that does not override the pullup or open drain
configuration for that pin).
When the pin muxing mode is configured for analog/disabled then the all digital
functions on that pin are disabled. This includes the pullup and pulldown enables, digital
output buffer enable, digital input buffer enable and passive filter enable.
• Pullup or pulldown enable
• Drive strength and slew rate configuration
• Open drain enable
• Passive input filter enable
• Pin muxing mode
A lock bit also exists that allows the configuration for each pin to be locked until the next
system reset. Once locked, writes to the lower half of that pin control register are ignored,
although a bus error is not generated on an attempted write to a locked register.
The configuration of each pin control register is retained when the PORT module is
disabled.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
266
Freescale Semiconductor, Inc.