K60P100M100SF2RM Datasheet, PDF (135/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

FTM0
CONF Register
GTBEOUT = 1
GTBEEN = 1
gtb_in
FTM Counter
gtb_out
FTM1
CONF Register
GTBEOUT = 0
GTBEEN = 1
gtb_in
FTM2
CONF Register
GTBEOUT = 0
GTBEEN = 1
gtb_in
Chapter 3 Chip Configuration
FTM Counter
FTM Counter
Figure 3-46. FTM Global Time Base Configuration
3.8.2.10 FTM BDM and debug halt mode
In the FTM chapter, references to the chip being in "BDM" are the same as the chip being
in “debug halt mode".
3.8.3 PIT Configuration
This section summarizes how the module has been configured in the chip. For a
comprehensive description of the module itself, see the module’s dedicated chapter.
Peripheral
bridge
Register
access
Periodic interrupt
timer
Topic
Full description
System memory map
Clocking
Power management
Figure 3-47. PIT configuration
Table 3-57. Reference links to related information
Related module
PIT
Reference
PIT
System memory map
Clock Distribution
Power management
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
135