K60P100M100SF2RM Datasheet, PDF (1611/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 52 Secured digital host controller (SDHC)
52.4.18 Watermark Level Register (SDHC_WML)
Both write and read watermark levels (FIFO threshold) are configurable. There value can
range from 1 to 128 words. Both write and read burst lengths are also configurable. There
value can range from 1 to 31 words.
Address: SDHC_WML is 400B_1000h base + 44h offset = 400B_1044h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
0
W
WRWML
0
0
RDWML
Reset 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0
SDHC_WML field descriptions
Field
31–29
Reserved
28–24
Reserved
23–16
WRWML
15–13
Reserved
12–8
Reserved
7–0
RDWML
Description
This read-only field is reserved and always has the value zero.
This read-only field is reserved and always has the value zero.
Write Watermark Level
The number of words used as the watermark level (FIFO threshold) in a DMA write operation. Also the
number of words as a sequence of write bursts in back-to-back mode. The maximum legal value for the
write watermark level is 128.
This read-only field is reserved and always has the value zero.
This read-only field is reserved and always has the value zero.
Read Watermark Level
The number of words used as the watermark level (FIFO threshold) in a DMA read operation. Also the
number of words as a sequence of read bursts in back-to-back mode. The maximum legal value for the
read water mark level is 128.
52.4.19 Force Event Register (SDHC_FEVT)
The force event register is not a physically implemented register. Rather, it is an address
at which the interrupt status register can be written if the corresponding bit of the
interrupt status enable register is set. This register is a write only register and writing 0 to
it has no effect. Writing 1 to this register actually sets the corresponding bit of interrupt
status register. A read from this register always results in 0's. In order to change the
corresponding status bits in the interrupt status register, make sure to set
SYSCTL[IPGEN] so that bus clock is always active.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1611