K60P100M100SF2RM Datasheet, PDF (397/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 18 Memory Protection Unit (MPU)
Table 18-81. Overlapping Region Descriptor Example (continued)
Region Description
RGDn
CP0
CP0 data & stack
2
rw-
CP0 → CP1 shared data
2
3
r--
CP1 → CP0 shared data
4
CP1 data & stack
4
—
Shared DMA data
5
rw-
MPU
6
rw-
Peripherals
7
rw-
CP1
DMA1
DMA2
—
—
—
r--
—
—
RAM
rw-
—
—
rw-
rw
rw
rw-
—
rw-
rw
—
Peripheral
—
space
In this example, there are eight descriptors used to span nine regions in the three main
spaces of the system memory map (flash, RAM, and peripheral space). Each region
indicates the specific permissions for each of the four bus masters and this definition
provides an appropriate set of shared, private and executable memory spaces.
Of particular interest are the two overlapping spaces: region descriptors 2 & 3 and 3 & 4.
The space defined by RGD2 with no overlap is a private data and stack area that provides
read/write access to CP0 only. The overlapping space between RGD2 and RGD3 defines
a shared data space for passing data from CP0 to CP1 and the access controls are defined
by the logical OR of the two region descriptors. Thus, CP0 has (rw- | r--) = (rw-)
permissions, while CP1 has (--- | r--) = (r--) permission in this space. Both DMA engines
are excluded from this shared processor data region. The overlapping spaces between
RGD3 and RGD4 defines another shared data space, this one for passing data from CP1
to CP0. For this overlapping space, CP0 has (r-- | ---) = (r--) permission, while CP1 has
(rw- | r--) = (rw-) permission. The non-overlapped space of RGD4 defines a private data
and stack area for CP1 only.
The space defined by RGD5 is a shared data region, accessible by all four bus masters.
Finally, the slave peripheral space mapped onto the IPS bus is partitioned into two
regions: one containing the MPU's programming model accessible only to the two
processor cores and the remaining peripheral region accessible to both processors and the
traditional DMA1 master.
This simple example is intended to show one possible application of the capabilities of
the MPU in a typical system.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
397