K60P100M100SF2RM Datasheet, PDF (738/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
FB_CLK
FB_A[Y]
Address
Add+1
Add+2
Add+3
FB_D[X]
Address
Data
Data
Data
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB_BE/BWEn
FB_TA
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ=11
Figure 29-51. 32-bit-Read Burst from 8-Bit Port 3-1-1-1 (Address Setup and Hold)
The following figure shows a write cycle with one clock of address setup and address
hold.
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
Address
Address
Add+1
Add+2
Data
Data
Data
Add+3
Data
AA=1
AA=0
TSIZ=11
AA=1
AA=0
Figure 29-52. 32-bit-Write Burst to 8-Bit Port 3-1-1-1 (Address Setup and Hold)
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
738
Freescale Semiconductor, Inc.