K60P100M100SF2RM Datasheet, PDF (275/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 12 System integration module (SIM)
SIM_SOPT2 field descriptions (continued)
Field
23–22
Reserved
21–20
TIMESRC
Description
10 OSCERCLK clock
11 External bypass clock (I2S0_CLKIN)
This read-only field is reserved and always has the value zero.
IEEE 1588 timestamp clock source select
Selects the clock source for the Ethernet timestamp clock.
19
Reserved
18
USBSRC
00 Core/system clock.
01 MCGPLLCLK/MCGFLLCLK clock
10 OSCERCLK clock
11 External bypass clock (ENET_1588_CLKIN).
This read-only field is reserved and always has the value zero.
USB clock source select
Selects the clock source for the USB 48 MHz clock.
17
Reserved
16
PLLFLLSEL
0 External bypass clock (USB_CLKIN).
1 MCGPLLCLK/MCGFLLCLK clock divided by the USB fractional divider. See the
SIM_CLKDIV2[USBFRAC, USBDIV] descriptions.
This read-only field is reserved and always has the value zero.
PLL/FLL clock select
Selects the MCGPLLCLK or MCGFLLCLK clock for various peripheral clocking options.
0 MCGFLLCLK clock
1 MCGPLLCLK clock
15–13
Reserved
This read-only field is reserved and always has the value zero.
12
Debug trace clock select
TRACECLKSEL
Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace clock source.
0 MCGOUTCLK
1 Core/system clock
11
CMTUARTPAD
CMT/UART pad drive strength
Controls the output drive strength of the CMT IRO signal or UART0_TXD signal on PTD7 pin by selecting
either one or two pads to drive it.
10
Reserved
9–8
FBSL
0 Single-pad drive strength for CMT IRO or UART0_TXD.
1 Dual-pad drive strength for CMT IRO or UART0_TXD.
This read-only field is reserved and always has the value zero.
FlexBus security level
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
275