K60P100M100SF2RM Datasheet, PDF (515/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 23
Watchdog Timer (WDOG)
23.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances see the chip configuration chapter.
The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it in
case of its failure. Some reasons for such failures are: run-away software code and the
stoppage of the system clock that in a safety critical system can lead to serious
consequences. In such cases, the watchdog brings the system into a safe state of
operation. The watchdog monitors the operation of the system by expecting periodic
communication from the software, generally known as servicing or refreshing the
watchdog. If this periodic refreshing does not occur, the watchdog resets the system.
23.2 Features
The features of the Watchdog Timer (WDOG) include:
• Independent clock source input (independent from CPU/bus clock). Choice between
two clock sources:
• LPO Oscillator
• External system clock
• Unlock sequence for allowing updates to write-once WDOG control/configuration
bits.
• All WDOG control/configuration bits are writable once only within 256 bus clock
cycles of being unlocked.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
515