K60P100M100SF2RM Datasheet, PDF (932/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

FTM Signal Descriptions
39.2 FTM Signal Descriptions
Table 39-1 shows the user-accessible signals for the FTM.
Table 39-1. FTM Signal Descriptions
Signal
Description
I/O
EXTCLK
External clock. FTM external clock can be selected to drive the FTM
I
counter.
CHn
FTM channel (n), where n can be 7-0
I/O
FAULTj
Fault input (j), where j can be 3-0
I
PHA
Quadrature decoder phase A input. Input pin associated with quadrature
I
decoder phase A.
PHB
Quadrature decoder phase B input. Input pin associated with quadrature
I
decoder phase B.
39.2.1 EXTCLK — FTM External Clock
The external clock input signal is used as the FTM counter clock if selected by
CLKS[1:0] bits in the SC register. This clock signal must not exceed 1/4 of system clock
frequency. The FTM counter prescaler selection and settings are also used when an
external clock is selected.
39.2.2 CHn — FTM Channel (n) I/O Pin
Each FTM channel can be configured to operate either as input or output. The direction
associated with each channel, input or output, is selected according to the mode assigned
for that channel.
39.2.3 FAULTj — FTM Fault Input
The fault input signals are used to control the CHn channel output state. If a fault is
detected, the FAULTj signal is asserted and the channel output is put in a safe state. The
behavior of the fault logic is defined by the FAULTM[1:0] control bits in the MODE
register and FAULTEN bit in the COMBINEm register. Note that each FAULTj input
may affect all channels selectively since FAULTM[1:0] and FAULTEN control bits are
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
932
Freescale Semiconductor, Inc.