K60P100M100SF2RM Datasheet, PDF (1571/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

• MMC 4-bit
• MMC 8-bit
• CE-ATA 1-bit
• CE-ATA 4-bit
• CE-ATA 8-bit
• Identification mode (up to 400 kHz)
• MMC full speed mode (up to 20 MHz)
• MMC high speed mode (up to 52 MHz)
• SD/SDIO full speed mode (up to 25 MHz)
• SD/SDIO high speed mode (up to 50 MHz)
Chapter 52 Secured digital host controller (SDHC)
52.3 SDHC signal descriptions
Table 52-1. SDHC signal descriptions
Signal
SDHC_DCLK
SDHC_CMD
SDHC_D0
SDHC_D1
SDHC_D2
SDHC_D3
SDHC_D4
SDHC_D5
Description
I/O
Generated clock used to drive the
O
MMC, SD, SDIO or CE-ATA cards.
Send commands to and receive
I/O
responses from the card.
DAT0 line or busy-state detect
I/O
8-bit mode: DAT1 line
I/O
4-bit mode: DAT1 line or interrupt
detect
1-bit mode: Interrupt detect
4-/8-bit mode: DAT2 line or read wait I/O
1-bit mode: Read wait
4-/8-bit mode: DAT3 line or configured I/O
as card detection pin
1-bit mode: May be configured as card
detection pin
DAT4 line in 8-bit mode
I/O
Not used in other modes
DAT5 line in 8-bit mode
I/O
Not used in other modes
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1571