K60P100M100SF2RM Datasheet, PDF (1099/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
Chapter 42 Carrier Modulator Transmitter (CMT)
CMT_DMA field descriptions (continued)
Description
0 DMA transfer request and done are disabled
1 _{DMA transfer request and done are enabled}
42.7 Functional Description
The CMT module consists primarily of clock divider, carrier generator and modulator.
42.7.1 Clock Divider
The CMT was originally designed to be based on 8 MHz bus clock that could be divided
by 1, 2, 4 or 8 times accordingly with the specification. To be compatible with higher bus
frequency, the Primary Prescaler (PPS) was developed to receive a higher frequency and
generate a clock enable signal called Intermediate Frequency (IF). This IF should be
approximately equal to 8 MHz and will work as a clock enable to the Secondary
Prescaler. The following figure shows the clock divider block diagram.
Bus clock
Primary
Prescaler
if_clk_enable
Secondary
Prescaler
divider_enable
Figure 42-14. Clock Divider Block Diagram
For compatibility with previous versions of CMT, when bus clock = 8 MHz, the PPS
should be configured to zero. The PPS counter is selected according to the bus clock to
generate an intermediate frequency approximately equal to 8 MHz.
42.7.2 Carrier Generator
The carrier generator resolution is 125 ns when operating with an 8 MHz intermediate
frequency signal and the Secondary Prescaler is set to divide by 1 (MSC[CMTDIV] =
00). The carrier generator can generate signals with periods between 250 ns (4 MHz) and
127.5 μs (7.84 kHz) in steps of 125 ns. The following table shows the relationship
between the clock divide bits and the carrier generator resolution, minimum carrier
generator period, and minimum modulator period.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1099