K60P100M100SF2RM Datasheet, PDF (182/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Clock definitions
Clock name
FlexBus clock
(FB_CLK)
Flash clock
Internal reference
(MCGIRCLK)
External reference
(OSCERCLK)
External reference
32kHz
(ERCLK32K)
RTC_CLKOUT
LPO
USB FS clock
I2S master clock
SDHC clock
Ethernet RMII clock
Table 5-1. Clock Summary (continued)
Run mode
clock frequency
Up to 50 MHz
Up to 25 MHz
30-40 kHz or 2 MHz
Up to 50 MHz
(bypass),
30-40 kHz, or
4-32 MHz (crystal)
30-40 kHz
1 Hz
1 kHz
48 MHz
Up to 50 MHz
Up to 50 MHz
50 MHz
VLPR mode
clock frequency
Up to 2 MHz
Up to 1 MHz
2 MHz only
Up to 4 MHz (bypass),
30-40 kHz (low-range
crystal) or
Up to 4 MHz (high-
range crystal)
30-40 kHz
1 Hz
1 kHz
N/A
N/A
N/A
N/A
Clock source
MCGOUTCLK clock
divider
MCGOUTCLK clock
divider
MCG
System OSC
System OSC or RTC
OSC depending on
SIM_SOPT1[OSC32K
SEL]
RTC clock
PMC
MCGPLLCLK or
MCGFLLCLK with
fractional clock divider,
or
USB_CLKIN
System clock,
MCGPLLCLK, or
MCGFLLCLK with
fractional clock divider,
OSCERCLK, or
I2S_CLKIN
System clock,
MCGPLLCLK/
MCGFLLCLK, or
OSCERCLK
OSCERCLK
Clock is disabled
when…
In all stop modes or
FlexBus disabled
In all stop modes
MCG_C1[IRCLKEN]
cleared,
Stop mode and
MCG_C1[IREFSTEN]
cleared, or
VLPS/LLS/VLLS mode
System OSC's
OSC_CR[ERCLKEN]
cleared, or
Stop mode and
OSC_CR[EREFSTEN]
cleared
System OSC's
OSC_CR[ERCLKEN]
cleared or
RTC's RTC_CR[OSCE]
cleared
Clock is disabled in
LLS and VLLSx modes
Available in all power
modes
USB FS OTG is
disabled
I²S is disabled
SDHC is disabled
Ethernet is disabled
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
182
Freescale Semiconductor, Inc.