K60P100M100SF2RM Datasheet, PDF (713/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Note
Chapter 29 External Bus Interface (FlexBus)
FB_TA does not have to be driven by the external device for
internally-terminated bus cycles.
Note
The processor drives the data lines during the first clock cycle
of the transfer with the full 32-bit address. This may be ignored
by standard connected devices using non-multiplexed address
and data buses. However, some applications may find this
feature beneficial.
The address and data busses are muxed between the FlexBus
and another module. At the end of the read bus cycles the
address signals are indeterminate.
FB_CLK
FB_A[Y]
Address
FB_D[X]
Address
Data
FB_RW
FB_TS
FB_ALE
AA=1
FB_CSn
AA=0
FB_OEn
FB_BE/BWEn
AA=1
FB_TA
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 29-27. Basic Read-Bus Cycle
29.4.6.2 Basic Write Bus Cycle
During a write cycle, the device sends data to memory or to a peripheral device. The
following figure shows the write cycle flowchart.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
713