K60P100M100SF2RM Datasheet, PDF (555/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 24 Multipurpose Clock Generator (MCG)
Table 24-14. MCG Modes of Operation (continued)
Mode
Description
FLL Bypassed External FLL bypassed external (FBE) mode is entered when all the following conditions occur:
(FBE)
• C1[CLKS] bits are written to 10
• C1[IREFS] bit is written to 0
• C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25
kHz to 39.0625 kHz.
• C6[PLLS] bit is written to 0
• C2[LP] is written to 0
In FBE mode, the MCGOUTCLK is derived from the OSCSEL external reference clock. The FLL is
operational but its output is not used. This mode is useful to allow the FLL to acquire its target
frequency while the MCGOUTCLK is driven from the external reference clock. The FLL clock
(DCOCLK) is controlled by the external reference clock, and the DCO clock frequency locks to a
multiplication factor, as selected by the C4[DRST_DRS] and C4[DMX32] bits, times the divided
external reference frequency. Refer to the C4[DMX32] bit description for more details. In FBI mode
the PLL is disabled in a low-power state unless C5[PLLCLKEN] is set.
PLL Engaged External PLL Engaged External (PEE) mode is entered when all the following conditions occur:
(PEE)
• C1[CLKS] bits are written to 00
• C1[IREFS] bit is written to 0
• C6[PLLS] bit is written to 1
In PEE mode, the MCGOUTCLK is derived from the PLL clock, which is controlled by the external
reference clock. The PLL clock frequency locks to a multiplication factor, as specified by C6[VDIV],
times the external reference frequency, as specified by C5[PRDIV]. The PLL's programmable
reference divider must be configured to produce a valid PLL reference clock. The FLL is disabled in
a low-power state.
PLL Bypassed External PLL Bypassed External (PBE) mode is entered when all the following conditions occur:
(PBE)
• C1[CLKS] bits are written to 10
• C1[IREFS] bit is written to 0
• C6[PLLS] bit is written to 1
• C2[LP] bit is written to 0
In PBE mode, MCGOUTCLK is derived from the OSCSEL external reference clock; the PLL is
operational, but its output clock is not used. This mode is useful to allow the PLL to acquire its
target frequency while MCGOUTCLK is driven from the external reference clock. The PLL clock
frequency locks to a multiplication factor, as specified by its [VDIV], times the PLL reference
frequency, as specified by its [PRDIV]. In preparation for transition to PEE, the PLL's programmable
reference divider must be configured to produce a valid PLL reference clock. The FLL is disabled in
a low-power state.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
555