K60P100M100SF2RM Datasheet, PDF (377/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 18
Memory Protection Unit (MPU)
18.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances see the chip configuration chapter.
The Memory Protection Unit (MPU) provides hardware access control for all memory
references generated in the device.
18.2 Overview
The MPU concurrently monitors all system bus transactions and evaluates their
appropriateness using pre-programmed region descriptors that define memory spaces and
their access rights. Memory references that have sufficient access control rights are
allowed to complete, while references that are not mapped to any region descriptor or
have insufficient rights are terminated with a protection error response.
18.2.1 Block Diagram
A simplified block diagram of the MPU module is shown in the following figure. The
hardware's two-dimensional connection matrix is clearly visible with the basic access
evaluation macro shown as the replicated submodule block. The crossbar switch slave
ports are shown on the left, the region descriptor registers in the middle, and the
peripheral bus interface on the right side. The evaluation macro contains two magnitude
comparators connected to the start and end address registers from each region descriptor
as well as the combinational logic blocks to determine the region hit and the access
protection error. For details of the access evaluation macro, see Access Evaluation
Macro.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
377