K60P100M100SF2RM Datasheet, PDF (1793/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 56 JTAG Controller (JTAGC)
scan register cell, as described in the IEEE 1149.1-2001 standard and discussed in
Boundary scan. The size of the boundary scan register and bit ordering is device-
dependent and can be found in the device BSDL file.
56.4 Functional description
This section explains the JTAGC functional description.
56.4.1 JTAGC reset configuration
While in reset, the TAP controller is forced into the Test-Logic-Reset state, thus disabling
the test logic and allowing normal operation of the on-chip system logic. In addition, the
instruction register is loaded with the IDCODE instruction.
56.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port
The JTAGC block uses the IEEE 1149.1-2001 TAP for accessing registers. This port can
be shared with other TAP controllers on the MCU. Ownership of the port is determined
by the value of the currently loaded instruction.
Data is shifted between TDI and TDO though the selected register starting with the least
significant bit, as illustrated in the following figure. This applies for the instruction
register, test data registers, and the bypass register.
MSB
LSB
TDI
Selected Register
TDO
Figure 56-3. Shifting data through a register
56.4.3 TAP controller state machine
The TAP controller is a synchronous state machine that interprets the sequence of logical
values on the TMS pin. The following figure shows the machine's states. The value
shown next to each state is the value of the TMS signal sampled on the rising edge of the
TCK signal. As the following figure shows, holding TMS at logic 1 while clocking TCK
through a sufficient number of rising edges also causes the state machine to enter the
Test-Logic-Reset state.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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