K60P100M100SF2RM Datasheet, PDF (1720/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional description
If receive FIFO 0 is enabled and receive interrupt enable (IER[RIE]) and received FIFO 0
full enable (IER[RDR0EN]) bits are set, receive interrupt 0 occurs when the received data
word is transferred to the receive FIFO 0 and receive FIFO 0 reaches the selected
threshold. This results in receive FIFO full 0 (RFF0) flag to set.
The core has to read the data from the receive data register 0 (RX0) (if receive FIFO 0 is
disabled) before a new data word is transferred from the receive shift register (RXSR).
Otherwise, the receive overrun error 0 (IER[ROE0EN]) bit is set. If receive FIFO 0 is
enabled, the receive overrun error 0 (ROE0) bit sets when the receive FIFO 0 data level
reaches the selected threshold and a new data word is ready to transfer to the receive
FIFO 0.
The following figure shows transmitter and receiver timing for an 8-bit word in the first
time slot in normal mode and continuous clock with a late word length frame sync. The
transmit data register is loaded with the data to be transmitted. On arrival of the clock,
this data is transferred to the transmit shift register which is transmitted on arrival of the
frame-sync on the STXD output. Simultaneously, the receive shift register shifts in the
received data available on the SRXD input. At the end of the time slot, this data is
transferred to the receive data register.
Continuos
CLK
FS
TX
DATA REG
STXD
SRXD
RX
DATA REG
Figure 53-46. Normal mode timing - continuous clock
The following figure shows a similar case for internal (I²S generates clock) gated clock
mode.
1720
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.