K60P100M100SF2RM Datasheet, PDF (509/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Address: EWM_CTRL is 4006_1000h base + 0h offset = 4006_1000h
Chapter 22 External Watchdog Monitor (EWM)
Bit
7
6
5
4
3
2
1
0
Read
0
Write
INEN
ASSIN
EWMEN
Reset
0
0
0
0
0
0
0
0
EWM_CTRL field descriptions
Field
7–3
Reserved
2
INEN
1
ASSIN
0
EWMEN
Description
This read-only field is reserved and always has the value zero.
Input Enable.
This bit when set, enables the EWM_in port.
EWM_in's Assertion State Select.
Default assert state of the EWM_in signal is logic zero. Setting ASSIN bit inverts the assert state to a logic
one.
EWM enable.
This bit when set, enables the EWM module. This resets the EWM counter to zero and deasserts the
EWM_out signal. Clearing EWMEN bit disables the EWM, and therefore it cannot be enabled until a reset
occurs, due to the write-once nature of this bit.
22.3.2 Service Register (EWM_SERV)
The SERV register provides the interface from the CPU to the EWM module. It is write-
only and reads of this register return zero.
Address: EWM_SERV is 4006_1000h base + 1h offset = 4006_1001h
Bit
7
6
5
4
3
2
1
0
Read
0
Write
SERVICE
Reset
0
0
0
0
0
0
0
0
EWM_SERV field descriptions
Field
7–0
SERVICE
Description
The EWM service mechanism requires the CPU to write two values to the SERV register: a first data byte
of 0xB4, followed by a second data byte of 0x2C. The EWM service is illegal if either of the following
conditions is true.
• The first or second data byte is not written correctly.
• The second data byte is not written within a fixed number of peripheral bus cycles of the first data
byte. This fixed number of cycles is called EWM_service_time.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
509