K60P100M100SF2RM Datasheet, PDF (1133/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

MII
1588_TMRn
ENET_1588_CLKIN
RMII
1588_TMRn
ENET_1588_CLKIN
Chapter 44 10/100-Mbps Ethernet MAC (ENET)
Description
I/O
Capture/compare block input/ I/O
output event bus. When
configured for capture and a
rising edge is detected, the
current timer value is latched
and transferred into the
corresponding ENET_TCCRn
register for inspection by
software.
When configured for
compare, the corresponding
signal 1588_TMRn is
asserted for one cycle when
the timer reaches the
compare value programmed
in register ENET_TCCRn.
An interrupt or DMA request
can be triggered if the
corresponding bit in
ENET_TCSRn[TIE] or
ENET_TCSRn[TDRE] is set.
Alternate IEEE 1588 Ethernet I
clock input
44.3 Memory Map/Register Definition
Reserved bits should be written with 0 and ignored on read to allow future extension.
Unused registers read zero and a write has no effect.
The following table summarizes the Ethernet registers.
Table 44-1. Register Map Summary
Offset Address
0x000
0x200
0x400
0x600
Section
Description
Configuration
Core control and status registers
Statistics counters MIB block counters. See Statistic Event Counters.
1588 control
1588 adjustable timer (TSM) and 1588 frame control
Capture/compare block Registers for the capture/compare block
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1133