K60P100M100SF2RM Datasheet, PDF (291/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
9
PORTA
8–7
Reserved
6
Reserved
5
TSI
4–2
Reserved
1
REGFILE
0
LPTIMER
Chapter 12 System integration module (SIM)
SIM_SCGC5 field descriptions (continued)
0 Clock disabled
1 Clock enabled
Port A Clock Gate Control
Description
This bit controls the clock gate to the Port A module.
0 Clock disabled
1 Clock enabled
This read-only field is reserved and always has the value one.
This read-only field is reserved and always has the value zero.
TSI Clock Gate Control
This bit controls the clock gate to the TSI module.
0 Clock disabled
1 Clock enabled
This read-only field is reserved and always has the value zero.
Register File Clock Gate Control
This bit controls the clock gate to the Register File module.
0 Clock disabled
1 Clock enabled
Low Power Timer Clock Gate Control
This bit controls the clock gate to the Low Power Timer module.
0 Clock disabled
1 Clock enabled
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
291