K60P100M100SF2RM Datasheet, PDF (433/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 21 Direct Memory Access Controller (eDMA)
• Channel completion reported via optional interrupt requests
• One interrupt per channel, optionally asserted at completion of major iteration
count
• Optional error terminations per channel and logically summed together to form
one error interrupt to the interrupt controller
• Optional support for scatter/gather DMA processing
• Support for complex data structures
• Support to cancel transfers via software
In the discussion of this module, n is used to reference the channel number.
21.2 Modes of operation
The eDMA operates in the following modes:
Table 21-3. Modes of operation
Normal
Mode
Debug
Wait
Description
In Normal mode, the eDMA transfers data between a source
and a destination. The source and destination can be a
memory block or an I/O block capable of operation with the
eDMA.
A service request initiates a transfer of a specific number of
bytes (NBYTES) as specified in the transfer control descriptor
(TCD). The minor loop is the sequence of read-write
operations that transfers these NBYTES per service request.
Each service request executes one iteration of the major
loop, which transfers NBYTES of data.
DMA operation is configurable in Debug mode via the control
register:
• If CR[EDBG] is cleared, the DMA continues to operate.
• If CR[EDBG] is set, the eDMA stops transferring data.
If Debug mode is entered while a channel is active, the
eDMA continues operation until the channel retires.
Before entering Wait mode, the DMA attempts to complete its
current transfer. After the transfer completes, the device
enters Wait mode.
21.3 Memory map/register definition
The eDMA's programming model is partitioned into two regions:
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
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