K60P100M100SF2RM Datasheet, PDF (1735/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 53 Integrated interchip sound (I2S)
53.4.2.1 I²S clock and frame sync generation
Data clock and frame sync signals can be generated internally, or can be obtained from
external sources. If internally generated, the I²S clock generator is used to derive bit
clock and frame sync signals from the network clock . The I²S clock generator consists of
a selectable, fixed prescaler and a programmable prescaler for bit rate clock generation.
In gated clock mode, the data clock is valid only when data is being transmitted.
Otherwise the clock port is pulled to the inactive state. A programmable frame rate
divider and a word length divider are used for frame rate sync signal generation.
The following figure shows a block diagram of the clock generator for the transmit
section. The serial bit clock can be internal or external, depending on the TCR[TXDIR]
bit. The receive section contains an equivalent clock generator circuit.
Network clock
DIV2
Divider
(/1 or /2)
PSR
Prescaler
(/1 or /8)
PM[7:0]
Divider
(/1 to /256)
Network clock (SRCK)
STCK
TXDIR
SYSCLKEN
TXDIR(1=output)
TXDIR(0=input)
TXDIR(1=output)
WL[3:0]
Word length
divider
Divide by
2
Word clock
Serial bit clock
Figure 53-56. I²S transmit clock generator block diagram
The following figure shows the frame sync generator block for the transmit section.
When internally generated, both receive and transmit frame sync are generated from the
word clock and are defined by the frame rate divider (DC) bits and the word length (WL)
bits of the TCCR. The receive section contains an equivalent circuit for the frame sync
generator.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1735