K60P100M100SF2RM Datasheet, PDF (1633/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

2. SD clock and monitor.
3. Command agent.
4. Data agent.
Chapter 52 Secured digital host controller (SDHC)
52.5.3.1 SD transceiver
In the SD protocol unit, the transceiver is the main control module. It consists of a FSM
and control module, from which the control signals for all other three modules are
generated.
52.5.3.2 SD clock & monitor
This module monitors the signal level on all 8 data lines, the command lines, and directly
routes the level values into the register bank. The driver can use this for debug purposes.
The module also detects the CD (card detection) line as well as the DAT[3] line. The
transceiver reports the card insertion state according to the CD state, or the signal level on
the DAT[3] line, when the PROCTL[D3CD] bit is set.
The module detects the WP (write protect) line. With the information of the WP state, the
register bank will ignore the command, accompanied by a write operation, when the WP
switch is on.
If the internal data buffer is in danger, and the SD clock must be gated off to avoid buffer
over/under-run, this module will assert the gate of the output SD clock to shut the clock
off. After the buffer danger has recovered, and when the system access of the buffer
catches up, the clock gate of this module will open and the SD clock will be active again.
This module also drive SDHC_LCTL output signal when the PROCTL[LCTL] bit is set
by the driver.
52.5.3.3 Command agent
The command agent deals with the transactions on the CMD line. The following diagram
illustrates the structure for the command CRC Shift Register.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1633