K60P100M100SF2RM Datasheet, PDF (1448/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map and Register Descriptions
I2Cx_F field descriptions
Field
7–6
MULT
Description
The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to generate
the I2C baud rate.
00 mul = 1
01 mul = 2
10 mul = 4
11 Reserved
5–0
Clock rate
ICR
Prescales the bus clock for bit rate selection. This field and the MULT field determine the I2C baud rate,
the SDA hold time, the SCL start hold time, and the SCL stop hold time. For a list of values corresponding
to each ICR setting, see I2C Divider and Hold Values.
The SCL divider multiplied by multiplier factor (mul) determines the I2C baud rate.
I2C baud rate = bus speed (Hz)/(mul × SCL divider)
The SDA hold time is the delay from the falling edge of SCL (I2C clock) to the changing of SDA (I2C
data).
SDA hold time = bus period (s) × mul × SDA hold value
The SCL start hold time is the delay from the falling edge of SDA (I2C data) while SCL is high (start
condition) to the falling edge of SCL (I2C clock).
SCL start hold time = bus period (s) × mul × SCL start hold value
The SCL stop hold time is the delay from the rising edge of SCL (I2C clock) to the rising edge of SDA (I2C
data) while SCL is high (stop condition).
SCL stop hold time = bus period (s) × mul × SCL stop hold value
50.3.3 I2C Control Register 1 (I2Cx_C1)
Addresses: I2C0_C1 is 4006_6000h base + 2h offset = 4006_6002h
I2C1_C1 is 4006_7000h base + 2h offset = 4006_7002h
Bit
Read
Write
Reset
7
IICEN
0
6
IICIE
0
5
MST
0
4
3
TX
TXAK
0
0
I2Cx_C1 field descriptions
Field
7
IICEN
I2C enable
Description
Enables I2C module operation.
Table continues on the next page...
2
0
RSTA
0
1
WUEN
0
0
DMAEN
0
1448
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.