K60P100M100SF2RM Datasheet, PDF (598/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory map and register descriptions
FMC_PFAPR field descriptions (continued)
Field
21
M5PFD
0 Prefetching for this master is enabled.
1 Prefetching for this master is disabled.
Master 5 Prefetch Disable
Description
These bits control whether prefetching is enabled based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
20
M4PFD
0 Prefetching for this master is enabled.
1 Prefetching for this master is disabled.
Master 4 Prefetch Disable
These bits control whether prefetching is enabled based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
19
M3PFD
0 Prefetching for this master is enabled.
1 Prefetching for this master is disabled.
Master 3 Prefetch Disable
These bits control whether prefetching is enabled based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
18
M2PFD
0 Prefetching for this master is enabled.
1 Prefetching for this master is disabled.
Master 2 Prefetch Disable
These bits control whether prefetching is enabled based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
17
M1PFD
0 Prefetching for this master is enabled.
1 Prefetching for this master is disabled.
Master 1 Prefetch Disable
These bits control whether prefetching is enabled based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
16
M0PFD
0 Prefetching for this master is enabled.
1 Prefetching for this master is disabled.
Master 0 Prefetch Disable
These bits control whether prefetching is enabled based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
15–14
M7AP[1:0]
0 Prefetching for this master is enabled.
1 Prefetching for this master is disabled.
Master 7 Access Protection
This field controls whether read and write access to the flash are allowed based on the logical master
number of the requesting crossbar switch master.
00 No access may be performed by this master.
01 Only read accesses may be performed by this master.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
598
Freescale Semiconductor, Inc.