K60P100M100SF2RM Datasheet, PDF (263/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 11 Port control and interrupts (PORT)
11.4.3 Global Pin Control High Register (PORTx_GPCHR)
Addresses: PORTA_GPCHR is 4004_9000h base + 84h offset = 4004_9084h
PORTB_GPCHR is 4004_A000h base + 84h offset = 4004_A084h
PORTC_GPCHR is 4004_B000h base + 84h offset = 4004_B084h
PORTD_GPCHR is 4004_C000h base + 84h offset = 4004_C084h
PORTE_GPCHR is 4004_D000h base + 84h offset = 4004_D084h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
0
W
GPWE
GPWD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORTx_GPCHR field descriptions
Field
31–16
GPWE
15–0
GPWD
Global Pin Write Enable
Description
When set, causes bits [15:0] of the corresponding Pin Control Register (31 through 16) to update with the
value in the Global Pin Write Data field.
Global Pin Write Data
Value to be written to bits [15:0] of all Pin Control Registers that are enabled by the Global Pin Write
Enable field, provided the corresponding register has not been locked.
11.4.4 Interrupt Status Flag Register (PORTx_ISFR)
The pin interrupt configuration is valid in all digital pin muxing modes. The Interrupt
Status Flag for each pin is also visible in the corresponding Pin Control Register, and
each flag can be cleared in either location.
Addresses: PORTA_ISFR is 4004_9000h base + A0h offset = 4004_90A0h
PORTB_ISFR is 4004_A000h base + A0h offset = 4004_A0A0h
PORTC_ISFR is 4004_B000h base + A0h offset = 4004_B0A0h
PORTD_ISFR is 4004_C000h base + A0h offset = 4004_C0A0h
PORTE_ISFR is 4004_D000h base + A0h offset = 4004_D0A0h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
ISF
W
w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
263