K60P100M100SF2RM Datasheet, PDF (1737/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 53 Integrated interchip sound (I2S)
In the next example, the oversampling clock (network clock) clock is 11.2896 MHz. A
16-bit word network mode with TCCR[DC] = 1, TCCR[PM] = 3, TCCR[PSR] = 0,
TCCR[DIV2] = 0, a bit clock rate of 1.4112 MHz is generated. Since the 16-bit word rate
is equal to two, the sampling rate (or frame sync rate) would be 1.4112/(2×16) = 44.1
kHz.
The following table shows examples of programming the TCCR[PSR] and TCCR[PM]
bits to generate various bit clock (STCK) frequencies.
Table 53-51. I²S bit clock and frame rate as a function of PSR, PM, and
DIV2
Bits/
word
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Words/
frame
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
MCLK/network clock
freq (MHz)
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
12.288
DIV2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TCCR
PSR PM WL DC
0
47 7 0
0
23 7 1
0
11 7 3
0
31 7 0
0
15 7 1
0
773
0
23 7 0
0
11 7 1
0
573
0
15 7 0
0
771
0
373
0
11 7 0
0
571
0
273
0
15 7 0
0
371
0
173
Bit clock
(kHz)
STCK
128
256
512
192
384
768
256
512
1024
384
768
1536
512
1024
2048
768
1536
3072
Frame
rate
(kHz)
8
8
8
12
12
12
16
16
16
24
24
24
32
32
32
48
48
48
16
1
16
2
16
4
16
1
16
2
16
4
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
0
0
31 7 0
0
0
15 7 1
0
0
773
0
0
15 7 0
0
0
771
0
0
373
Table continues on the next page...
176.4
352.8
705.6
352.8
705.6
1411.2
11.025
11.025
11.025
22.05
22.05
22.05
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1737