K60P100M100SF2RM Datasheet, PDF (1585/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
15–12
Reserved
11
BREN
10
BWEN
9
RTA
8
WTA
Chapter 52 Secured digital host controller (SDHC)
SDHC_PRSSTAT field descriptions (continued)
Description
The SYSCTL[RSTA] does not effect this bit.A software reset does not effect this bit.
0b Power on reset or no card
1b Card inserted
This read-only field is reserved and always has the value zero.
Buffer Read Enable
This status bit is used for non-DMA read transfers. The SDHC may implement multiple buffers to transfer
data efficiently. This read only flag indicates that valid data exists in the host side buffer. If this bit is high,
valid data greater than the watermark level exist in the buffer. This read only flag indicates that valid data
exists in the host side buffer.
0b Read disable, valid data less than the watermark level exist in the buffer.
1b Read enable, valid data greater than the watermark level exist in the buffer.
Buffer Write Enable
This status bit is used for non-DMA write transfers. The SDHC can implement multiple buffers to transfer
data efficiently. This read only flag indicates if space is available for write data. If this bit is 1, valid data
greater than the watermark level can be written to the buffer.This read only flag indicates if space is
available for write data.
0b Write disable, the buffer can hold valid data less than the write watermark level.
1b Write enable, the buffer can hold valid data greater than the write watermark level.
Read Transfer Active
This status bit is used for detecting completion of a read transfer.
This bit is set for either of the following conditions:
• After the end bit of the read command.
• When writing a 1 to the PROCTL[CREQ] to restart a read transfer.
A transfer complete interrupt is generated when this bit changes to 0. This bit is cleared for either of the
following conditions:
• When the last data block as specified by block length is transferred to the system, that is all data
are read away from SDHC internal buffer.
• When all valid data blocks have been transferred from SDHC internal buffer to the system and no
current block transfers are being sent as a result of the stop at block gap request being set to 1.
0b No valid data
1b Transferring data
Write Transfer Active
This status bit indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the
SDHC.
This bit is set in either of the following cases:
• After the end bit of the write command.
• When writing 1 to the PROCTL[CREQ] to restart a write transfer.
This bit is cleared in either of the following cases:
• After getting the CRC status of the last data block as specified by the transfer count (single and
multiple).
• After getting the CRC status of any block where data transmission is about to be stopped by a stop
at block gap request.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1585