K60P100M100SF2RM Datasheet, PDF (61/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 2 Introduction
2.3.1 ARM Cortex-M4 Core Modules
The following core modules are available on this device.
Table 2-2. Core modules
Module
ARM Cortex-M4
NVIC
AWIC
Debug interfaces
Description
The ARM Cortex-M4 is the newest member of the Cortex M Series of processors
targeting microcontroller cores focused on very cost sensitive, deterministic,
interrupt driven environments. The Cortex M4 processor is based on the ARMv7
Architecture and Thumb®-2 ISA and is upward compatible with the Cortex M3,
Cortex M1, and Cortex M0 architectures. Cortex M4 improvements include an
ARMv7 Thumb-2 DSP (ported from the ARMv7-A/R profile architectures) providing
32-bit instructions with SIMD (single instruction multiple data) DSP style multiply-
accumulates and saturating arithmetic.
The ARMv7-M exception model and nested-vectored interrupt controller (NVIC)
implement a relocatable vector table supporting many external interrupts, a single
non-maskable interrupt (NMI), and priority levels.
The NVIC replaces shadow registers with equivalent system and simplified
programmability. The NVIC contains the address of the function to execute for a
particular handler. The address is fetched via the instruction port allowing parallel
register stacking and look-up. The first sixteen entries are allocated to ARM
internal sources with the others mapping to MCU-defined interrupts.
The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is
to detect asynchronous wake-up events in stop modes and signal to clock control
logic to resume system clocking. After clock restart, the NVIC observes the
pending interrupt and performs the normal interrupt or event processing.
Most of this device's debug is based on the ARM CoreSight^™ architecture. Four
debug interfaces are supported:
• IEEE 1149.1 JTAG
• IEEE 1149.7 JTAG (cJTAG)
• Serial Wire Debug (SWD)
• ARM Real-Time Trace Interface
2.3.2 System Modules
The following system modules are available on this device.
Table 2-3. System modules
Module
System integration module (SIM)
Mode controller
Description
The SIM includes integration logic and several module configuration settings.
The MC provides control and protection on entry and exit to each power mode,
control for the Power management controller (PMC), and reset entry and exit for
the complete MCU.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
61