K60P100M100SF2RM Datasheet, PDF (1165/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 44 10/100-Mbps Ethernet MAC (ENET)
44.3.33 Timer Control Register (ENET_ATCR)
ATCR command bits can trigger the corresponding events directly. It is not necessary to
preserve any of the configuration bits when a command bit is set in the register (no read-
modify-write is required). The bits are automatically cleared after the command
completes.
Address: ENET_ATCR is 400C_0000h base + 400h offset = 400C_0400h
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
W
0
EN
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ENET_ATCR field descriptions
Field
31–14
Reserved
13
SLAVE
12
Reserved
11
CAPTURE
10
Reserved
9
RESTART
Description
This read-only field is reserved and always has the value zero.
Enable timer slave mode
0 The timer is active and all configuration bits in this register are relevant.
1 The internal timer is disabled and the externally provided timer value is used. All other bits, except
CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer
value.
This read-only field is reserved and always has the value zero.
Capture timer value
0 No effect.
1 The current time is captured and can be read from the ATVR register.
This read-only field is reserved and always has the value zero.
Reset timer
Resets the timer to zero. This has no effect on the counter enable. If the counter is enabled when this bit
is set, the timer is reset to zero and starts counting from there. When set, all other bits are ignored during
a write.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1165