K60P100M100SF2RM Datasheet, PDF (1650/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Initialization/application of SDHC
1. Check the card status, wait until card is ready for data.
2. Set the card block length/size:
a. For SD/MMC, use SET_BLOCKLEN (CMD16)
b. For SDIO cards or the I/O portion of SDCombo cards, use
IO_RW_DIRECT(CMD52) to set the I/O Block Size bit field in the CCCR
register (for function 0) or FBR register (for functions 1~7)
c. For CE-ATA cards, configure bits 1~0 in the scrControl register
3. Set the SDHC block length register to be the same as the block length set for the card
in Step 2.
4. Set the SDHC number block register (NOB), nob is 5 (for instance).
5. Disable the buffer write ready interrupt, configure the DMA settings and enable the
SDHC DMA when sending the command with data transfer. The
XFERTYP[AC12EN] bit should also be set.
6. Set the PROCTL[SABGREQ] bit.
7. Wait for the transfer complete interrupt.
8. Clear the PROCTL[SABGREQ] bit.
9. Check the status bit to see if a write CRC error occurred.
10. Set the PROCTL[CREQ] bit to continue the write operation.
11. Wait for the transfer complete interrupt.
12. Check the status bit to see if a write CRC error occurred, or some another error, that
occurred during the auto12 command sending and response receiving.
The number of blocks left during the data transfer is accessible by reading the contents of
the BLKATTR[BLKCNT] . As the data transfer and the setting of the
PROCTL[SABGREQ] bit are concurrent, and the delay of register read and the register
setting, the actual number of blocks left may not be exactly the value read earlier. The
driver shall read the value of BLKATTR[BLKCNT] after the transfer is paused and the
transfer complete interrupt is received.
It is also possible the last block has begun when the stop at block gap request is sent to
the buffer. In this case, the next block gap is actually the end of the transfer. These types
of requests are ignored and the Driver should treat this as a non-pause transfer and deal
with it as a common write operation.
1650
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.