K60P100M100SF2RM Datasheet, PDF (1445/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Module Enable Address
ADDR_DECODE
Chapter 50 Inter-Integrated Circuit (I2C)
Interrupt
Write/Read
DATA_MUX
CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG
Input
Sync
Clock
Control
START
STOP
Arbitration
Control
In/Out
Data
Shift
Register
Address
Compare
SCL
SDA
Figure 50-1. I2C Functional Block Diagram
50.2 I²C Signal Descriptions
The signal properties of I²C are shown in the following table.
Table 50-1. I²C Signal Descriptions
Signal
Description
I/O
SCL
Bidirectional serial clock line of the I²C system.
I/O
SDA
Bidirectional serial data line of the I²C system.
I/O
50.3 Memory Map and Register Descriptions
This section describes in detail all I2C registers accessible to the end user.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1445