K60P100M100SF2RM Datasheet, PDF (544/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Memory Map/Register Definition
MCG_C2 field descriptions (continued)
Field
0
IRCS
Description
0 FLL (or PLL) is not disabled in bypass modes.
1 FLL (or PLL) is disabled in bypass modes (lower power)
Internal Reference Clock Select
Selects between the fast or slow internal reference clock source.
0 Slow internal reference clock selected.
1 Fast internal reference clock selected.
24.3.3 MCG Control 3 Register (MCG_C3)
Address: MCG_C3 is 4006_4000h base + 2h offset = 4006_4002h
Bit
7
6
5
4
3
2
1
0
Read
Write
SCTRIM
Reset
x*
x*
x*
x*
x*
x*
x*
x*
* Notes:
• x = Undefined at reset.
Field
7–0
SCTRIM
MCG_C3 field descriptions
Description
Slow Internal Reference Clock Trim Setting
SCTRIM ¹ controls the slow internal reference clock frequency by controlling the slow internal reference
clock period. The SCTRIM bits are binary weighted (that is, bit 1 adjusts twice as much as bit 0).
Increasing the binary value increases the period, and decreasing the value decreases the period.
An additional fine trim bit is available in C4 register as the SCFTRIM bit. Upon reset this value is loaded
with a factory trim value.
If an SCTRIM value stored in nonvolatile memory is to be used, it is your responsibility to copy that value
from the nonvolatile memory location to this register.
1. A value for SCTRIM is loaded during reset from a factory programmed location .
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
544
Freescale Semiconductor, Inc.