K60P100M100SF2RM Datasheet, PDF (152/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Communication interfaces
3.9.4.6 Number of PCS signals
The following table shows the number of peripheral chip select signals available per SPI
module.
Table 3-70. SPI PCS signals
SPI Module
SPI0
SPI1
SPI2
PCS Signals
SPI_PCS[5:0]
SPI_PCS[3:0]
SPI_PCS[1:0]
3.9.4.7 SPI Operation in Low Power Modes
In VLPR and VLPW modes the SPI is functional; however, the reduced system
frequency also reduces the max frequency of operation for the SPI. In VLPR and VLPW
modes the max SPI_CLK frequency is 1MHz.
In stop and VLPS modes, the clocks to the SPI module are disabled. The module is not
functional, but it is powered so that it retains state.
There is one way to wake from stop mode via the SPI, which is explained in the
following section.
3.9.4.7.1 Using GPIO Interrupt to Wake from stop mode
Here are the steps to use a GPIO to create a wakeup upon reception of SPI data in slave
mode:
1. Point the GPIO interrupt vector to the desired interrupt handler.
2. Enable the GPIO input to generate an interrupt on either the rising or falling edge
(depending on the polarity of the chip select signal).
3. Enter Stop or VLPS mode and Wait for the GPIO interrupt.
NOTE
It is likely that in using this approach the first word of data from
the SPI host might not be received correctly. This is dependent
on the transfer rate used for the SPI, the delay between chip
select assertion and presentation of data, and the system
interrupt latency.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
152
Freescale Semiconductor, Inc.