K60P100M100SF2RM Datasheet, PDF (1466/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
the I2C module is an active master, if it detects that SMBCLK low has exceeded the
value of T_TIMEOUT,MIN, it must generate a stop condition within or after the current data
byte in the transfer process. When the I2C module is a slave, if it detects the
T_TIMEOUT,MIN condition, it resets its communication and is then able to receive a new
START condition.
50.4.4.1.2 SCL High Timeout
When the I2C module has determined that the SMBCLK and SMBDAT signals have
been high for at least T_HIGH:MAX, it assumes that the bus is idle. A HIGH timeout can
occur in two ways:
1. HIGH timeout detected after a STOP condition appears on the bus
2. HIGH timeout detected after a START condition, but before a STOP condition
appears on the bus
Any master detecting either scenario can assume the bus is free when SHTF1 rises. A
HIGH timeout occurs in scenario 2 if a master ever detects that both the BUSY bit is high
and SHTF1 is high.
When the SMBDAT signal is low and the SMBCLK signal is high for a period of time,
the other kind of timeout occurs. The time period must be defined in software. SHTF2 is
used as the flag when the time limit is reached. This flag is also an interrupt resource, so
it also triggers IICIF.
50.4.4.1.3 CSMBCLK TIMEOUT MEXT and CSMBCLK TIMEOUT SEXT
The following figure illustrates the definition of the timeout intervals T_LOW:SEXT and
T_LOW:MEXT. When in master mode, the I2C module must not cumulatively extend its
clock cycles for a period greater than T_LOW:MEXT within a byte, where each byte is
defined as START-to-ACK, ACK-to-ACK, or ACK-to-STOP. When CSMBCLK
TIMEOUT MEXT occurs, SMBus MEXT rises and also triggers the SLTF.
1466
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.