K60P100M100SF2RM Datasheet, PDF (1309/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 48 CAN (FlexCAN)
It is enabled when the FRZ bit in the MCR Register is asserted. If enabled, Freeze
Mode is entered when the HALT bit in MCR is set or when Debug Mode is
requested at MCU level and the FRZ_ACK bit in the MCR Register is asserted by
the FlexCAN. In this mode, no transmission or reception of frames is done and
synchronicity to the CAN bus is lost. See Freeze Mode for more information.
• Listen-Only Mode:
The module enters this mode when the LOM bit in the Control 1 Register is asserted.
In this mode, transmission is disabled, all error counters are frozen and the module
operates in a CAN Error Passive mode. Only messages acknowledged by another
CAN station will be received. If FlexCAN detects a message that has not been
acknowledged, it will flag a BIT0 error (without changing the REC), as if it was
trying to acknowledge the message.
• Loop-Back Mode:
The module enters this mode when the LPB bit in the Control 1 Register is asserted.
In this mode, FlexCAN performs an internal loop back that can be used for self test
operation. The bit stream output of the transmitter is internally fed back to the
receiver input. The Rx CAN input pin is ignored and the Tx CAN output goes to the
recessive state (logic '1'). FlexCAN behaves as it normally does when transmitting
and treats its own transmitted message as a message received from a remote node. In
this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN frame
acknowledge field to ensure proper reception of its own message. Both transmit and
receive interrupts are generated.
• Module Disable Mode:
This low power mode is entered when the MDIS bit in the MCR Register is asserted
by the CPU and the LPM_ACK is asserted by the FlexCAN. When disabled, the
module requests to disable the clocks to the CAN Protocol Engine and Controller
Host Interface sub-modules. Exit from this mode is done by negating the MDIS bit in
the MCR Register. See Module Disable Mode for more information.
• Doze Mode:
This low power mode is entered when the DOZE bit in MCR is asserted and Doze
Mode is requested at MCU level and the LPM_ACK bit in the MCR Register is
asserted by the FlexCAN. When in Doze Mode, the module requests to disable the
clocks to the CAN Protocol Engine and the CAN Controller-Host Interface sub-
modules. Exit from this mode happens when the DOZE bit in MCR is negated, when
the MCU is removed from Doze Mode, or when activity is detected on the CAN bus
and the Self Wake Up mechanism is enabled. See Doze Mode for more information.
• Stop Mode:
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1309