K60P100M100SF2RM Datasheet, PDF (1382/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Functional Description
The Bus Interface Unit continues to operate, enabling the CPU to access memory mapped
registers, except the Rx Mailboxes Global Mask Registers, the Rx Buffer 14 Mask
Register, the Rx Buffer 15 Mask Register, the Rx FIFO Global Mask Register. The Rx
FIFO Information Register, the Message Buffers, the Rx Individual Mask Registers, and
the reserved words within RAM may not be accessed when the module is in Disable
Mode. Exiting from this mode is done by negating the MDIS bit by the CPU, which
causes the FlexCAN to request to resume the clocks and negate the LPM_ACK bit after
the CAN protocol engine recognizes the negation of disable mode requested by the CPU.
48.4.9.3 Doze Mode
This is a system low power mode in which the CPU bus is kept alive and a global Doze
Mode request is sent to all peripherals asking them to enter low power mode. When Doze
Mode is globally requested, the DOZE bit in MCR Register needs to have been asserted
previously for Doze Mode to be triggered. The acknowledgement is obtained through the
assertion by the FlexCAN of the LPM_ACK bit in the same register. The CPU must only
consider the FlexCAN in Doze Mode when both request and acknowledgement
conditions are satisfied.
If Doze Mode is triggered during Freeze Mode, FlexCAN requests to shut down the
clocks to the PE and CHI sub-modules, sets the LPM_ACK bit and negates the
FRZ_ACK bit. If Doze Mode is triggered during transmission or reception, FlexCAN
does the following:
• Waits to be in either Idle or Bus Off state, or else waits for the third bit of
Intermission and checks it to be recessive
• Waits for all internal activities like arbitration, matching, move-in and move-out to
finish. A pending move-in is not taken into account.
• Ignores its Rx input pin and drives its Tx pin as recessive
• Shuts down the clocks to the PE and CHI sub-modules
• Sets the NOT_RDY and LPM_ACK bits in MCR
The Bus Interface Unit continues to operate, enabling the CPU to access memory mapped
registers, except the Rx Mailboxes Global Mask Registers, the Rx Buffer 14 Mask
Register, the Rx Buffer 15 Mask Register, the Rx FIFO Global Mask Register. The Rx
FIFO Information Register, the Message Buffers, the Rx Individual Mask Registers, and
the reserved words within RAM may not be accessed when the module is in Doze Mode.
Exiting Doze Mode is done in one of the following ways:
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K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.