K60P100M100SF2RM Datasheet, PDF (1607/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

• Check errors correspond to bits 1-4.
Chapter 52 Secured digital host controller (SDHC)
• Set bits 1-4 corresponding to detected errors.
• Clear bits 1-4 corresponding to detected errors.
3. Before reading the auto CMD12 error status bit 7.
• Set bit 7 to 1 if there is a command that can't be issued.
• Clear bit 7 if there is no command to issue.
The timing for generating the auto CMD12 error and writing to the command register are
asynchronous. After that, bit 7 shall be sampled when the driver is not writing to the
command register. So it is suggested to read this register only when the
IRQSTAT[AC12E] is set. An Auto CMD12 error interrupt is generated when one of the
error bits (0-4) is set to 1. The command not issued by auto CMD12 error does not
generate an interrupt.
Address: SDHC_AC12ERR is 400B_1000h base + 3Ch offset = 400B_103Ch
Bit 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit 15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
W
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SDHC_AC12ERR field descriptions
Field
31–8
Reserved
Description
This read-only field is reserved and always has the value zero.
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1607