K60P100M100SF2RM Datasheet, PDF (1673/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

52.7.5 (A)DMA address setting
Chapter 52 Secured digital host controller (SDHC)
To configure ADMA1/ADMA2/DMA address register, when TC[IRQSTAT] bit is set,
the register will always update itself with the internal address value to support dynamic
address synchronization, so software must make sure TC[IRQSTAT] bit is cleared prior
to configuring ADMA1/ADMA2/DMA address register.
52.7.6 Data port access
Data port does not support parallel access. For example, during an external DMA access,
it is not allowed to write any data to the data port by CPU; or during a CPU read
operation, it is also prohibited to write any data to the data port, by either CPU or external
DMA. Otherwise the data would be corrupted inside the SDHC buffer.
52.7.7 Change clock frequency
SDHC does not automatically gates off the card clock when the host driver changes the
clock frequency. To remove possible glitch on the card clock, clear
SYSCTL[SDCLKEN] bit when changing clock divisor value and set
SYSCTL[SDCLKEN] bit to '1' after PRSSTAT[SDSTB] bit is '1' again.
52.7.8 Multi-block read
For pre-defined multi-block read operation, i.e., the number of blocks to read has been
defined by previous CMD23 for MMC, or pre-defined number of blocks in CMD53 for
SDIO/SDCombo, or whatever multi-block read without abort command at card side, an
abort command, either automatic or manual CMD12/CMD52, is still required by SDHC
after the pre-defined number of blocks are done, to drive the internal start response
timeout. It is recommended to manually send an abort command with
XFERTYP[RSPTYP] both bits cleared.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1673