K60P100M100SF2RM Datasheet, PDF (1741/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 53 Integrated interchip sound (I2S)
Table 53-54. I²S receive data interrupts
Interrupt
RIE
Receive data 0 interrupts (n = 0)
Receive data 0 (with exception status)
1
Receive data 0 (without exception)
1
Receive data 1 interrupts (n = 1)
Receive data 1 (with exception status)
1
Receive data 1 (without exception)
1
ROEn
1
0
1
0
RFFn/RDRn
1
1
1
1
53.4.5 Transmit interrupt enable bit description
If the transmit FIFO is not enabled and the IER[TIE] and CR[TE] bits are set:
• an interrupt occurs when the corresponding I²S transmit data register empty
(ISR[TDE0/1]) flag is set
• one value can be written to the I²S_TX0 register (one per channel, in two-channel
mode using I²S_TX1)
If the transmit FIFO is enabled and the IER[TIE] and CR[TE] bits are set:
• an interrupt occurs when either of the I²S transmit FIFO empty (ISR[TFE0/1]) flags
is set
• a maximum of 15 values can be written to the I²S ( 15 per channel in two-channel
mode, using Tx FIFO 1)
When the IER[TIE] bit is cleared, all transmit interrupts are disabled. However, the
ISR[TDE0/1] bits always indicate the corresponding TX register empty condition, even
when the transmitter is disabled by the transmit enable (CR[TE]) bit. Writing data to the
TX clears the corresponding ISR[TDE] bit, thus clearing the interrupt.
Two transmit data interrupts are available (four in two-channel mode, two per channel):
transmit data with exception status and transmit data without exceptions. The following
table shows the conditions under which these interrupts are generated.
Table 53-55. I²S transmit data interrupts
Interrupt
TIE
Transmit data 0 interrupts (n = 0)
Transmit data 1 (with exception status)
1
TUEn
1
TFEn/TDEn
1
Table continues on the next page...
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1741