K60P100M100SF2RM Datasheet, PDF (1401/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Field
13
DIS_TXF
12
DIS_RXF
11
CLR_TXF
10
CLR_RXF
9–8
SMPL_PT
7–2
Reserved
1
Reserved
0
HALT
SPIx_MCR field descriptions (continued)
Chapter 49 SPI (DSPI)
Disable Transmit FIFO
Description
When the TX FIFO is disabled, the transmit part of the DSPI operates as a simplified double-buffered SPI.
This bit can only be written when the MDIS bit is cleared.
0 Tx FIFO is enabled.
1 Tx FIFO is disabled.
Disable Receive FIFO
When the RX FIFO is disabled, the receive part of the DSPI operates as a simplified double-buffered SPI.
This bit can only be written when the MDIS bit is cleared.
0 Rx FIFO is enabled.
1 Rx FIFO is disabled.
Clear TX FIFO
Flushes the TX FIFO. Writing a 1 to CLR_TXF clears the TX FIFO Counter. The CLR_TXF bit is always
read as zero.
0 Do not clear the Tx FIFO counter.
1 Clear the Tx FIFO counter.
Flushes the RX FIFO. Writing a 1 to CLR_RXF clears the RX Counter. The CLR_RXF bit is always read
as zero.
0 Do not clear the Rx FIFO counter.
1 Clear the Rx FIFO counter.
Sample Point
Controls when the DSPI master samples SIN in Modified Transfer Format. This field is valid only when
CPHA bit in CTAR register is 0.
00 0 system clocks between SCK edge and SIN sample
01 1 system clock between SCK edge and SIN sample
10 2 system clocks between SCK edge and SIN sample
11 Reserved
This read-only field is reserved and always has the value zero.
This read-only field is reserved and always has the value zero.
Halt
Starts and stops DSPI transfers.
0 Start transfers.
1 Stop transfers.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
1401