K60P100M100SF2RM Datasheet, PDF (463/1809 Pages) Freescale Semiconductor, Inc – K60 Sub-Family Reference Manual

Chapter 21 Direct Memory Access Controller (eDMA)
21.3.12 Clear Interrupt Request Register (DMA_CINT)
The CINT provides a simple, memory-mapped mechanism to clear a given bit in the INT
to disable the interrupt request for a given channel. The given value on a register write
causes the corresponding bit in the INT to be cleared. Setting the CAIR bit provides a
global clear function, forcing the entire contents of the INT to be cleared, disabling all
DMA interrupt requests. If the NOP bit is set, the command is ignored. This allows you
to write multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
Address: DMA_CINT is 4000_8000h base + 1Fh offset = 4000_801Fh
Bit
7
6
5
4
3
2
1
0
Read
0
0
0
Write
NOP
CAIR
0
CINT
Reset
0
0
0
0
0
0
0
0
DMA_CINT field descriptions
Field
7
NOP
6
CAIR
5–4
Reserved
3–0
CINT
Description
0 Normal operation
1 No operation, ignore the other bits in this register
Clear All Interrupt Requests
0 Clear only the INT bit specified in the CINT field
1 Clear all bits in INT
This field is reserved.
Clear Interrupt Request
Clears the corresponding bit in INT
21.3.13 Interrupt Request Register (DMA_INT)
The INT register provides a bit map for the 16 channels signaling the presence of an
interrupt request for each channel. Depending on the appropriate bit setting in the
transfer-control descriptors, the eDMA engine generates an interrupt on data transfer
completion. The outputs of this register are directly routed to the interrupt controller
(INTC). During the interrupt-service routine associated with any given channel, it is the
software’s responsibility to clear the appropriate bit, negating the interrupt request.
Typically, a write to the CINT register in the interrupt service routine is used for this
purpose.
K60 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
463